Open-source high-performance RISC-V processor
Scala 7.4k 977
Documentation for XiangShan
Markdown 448 154
Open-source high-performance non-blocking cache
Scala 102 40
Modern co-simulation framework for RISC-V CPUs
C++ 191 114
XiangShan Frontend Develop Environment
Shell 76 78
Super fast RISC-V ISA emulator for XiangShan processor
C 354 147
A fork of XSCache for XSAI. Supports High-Bandwidth L2 Cache design.
Trace-driven CPU RTL performance evaluation for robust simulation, broad application coverage, and rapid prototyping.
Scripts for XiangShan
The Unified TileLink Memory Subsystem Tester for XiangShan
Open-source L2 (RN) & LLC (HN) cache for XiangShan open-source RISC-V core. Supports CHI Issue B/C/E.b protocols.
A fork of Xiangshan for AI