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alveo

Here are 18 public repositories matching this topic...

Vitis_Accel_Examples

Xilinx / Vitis_Accel_Examples

Vitis_Accel_Examples

zynq xilinx soc alveo fpga-programming acap vitis

Updated Aug 31, 2026
Makefile

Xilinx / finn-examples

Dataflow QNN inference accelerator examples on FPGAs

fpga pynq alveo finn neural-network-accelerators

Updated Mar 10, 2026
Python

Xilinx / xup_vitis_network_example

VNx: Vitis Network Examples

networking xilinx alveo vnx vitis vitis-network alveo-card

Updated Aug 25, 2025
Jupyter Notebook

Xilinx / ResNet50-PYNQ

Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ

python xilinx pynq alveo finn

Updated Nov 23, 2021
C++

Xilinx / Alveo-PYNQ

Introductory examples for using PYNQ with Alveo

xilinx pynq alveo aws-f1

Updated Mar 14, 2023
Jupyter Notebook

ECASLab / cynq

PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.

linux fpga runtime amd xilinx pynq artix7 alveo cynq

Updated Apr 9, 2026
C++

MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow

Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.

fpga xilinx pynq alveo pynq-z2 alveo-u200

Updated Apr 28, 2020
Jupyter Notebook

fpgasystems / erbium

Business Rule Engine Hardware Accelerator

fpga rule-engine nfa search-engine-optimization alveo aws-f1

Updated Jun 18, 2020
VHDL

Gabriele-bot / ALVEO-PYNQ_ML

Neural network inferences on Alveo cards with hls4ml framework

machine-learning fpga xilinx-fpga alveo tensorflow2 hls4ml

Updated Jul 28, 2022
Ada

Xilinx / 5point-PYNQ

5-point Relative Pose Problem for PYNQ

python xilinx pynq alveo

Updated Feb 27, 2020
C

DYGV / FPGA-Based-EdgeAI-Prototypes

Xilinx DPU(Vitis AI)を用いたエッジAI実現に向けたサンプルプログラム

machine-learning fpga embedded-systems petalinux edge-computing alveo edge-ai vitis-ai ai-embedded-systems zynq-ultrascale deep-learning-processor-unit

Updated Aug 15, 2023
C++

andrea-zanette / HippoScan

A framework to train a ResUNet architecture, quantize, compile and execute it on an FPGA.

fpga keras segmentation pynq alveo tensorflow2 resunet post-training-quantization vitis-ai ultra96v2

Updated Jun 23, 2023
Jupyter Notebook

nixir / callAlveoFromMATLAB

This Repo contains a programs of calling Xilinx Alveo accelerator card from MATLAB

fpga matlab alveo alveo-u200 alveo-u280

Updated Oct 29, 2020
C

Alveo / alveo-transcriber

Web application to transcribe data for the Alveo project

angular offline-first wavesurfer alveo

Updated Jan 5, 2019
TypeScript

Accelize / nimbix_drm_demo

This demo is intended to demonstrate the FPGA design protection and metering capability provided by the Accelize Distribution Platform.

fpga xilinx-fpga rights-management bitstream alveo

Updated May 6, 2019
C++

todi-mih / mamba790m_hls

A full Mamba (SSM) block on the Xilinx Alveo U55N in Vitis HLS, verified bit-exact against the PyTorch reference

fpga hls mamba alveo vitis vitis-ai vitis-hls

Updated Jul 3, 2026
C++

Karakchi-Research / BASE

Reusable FPGA streaming preprocessing accelerator for byte-level statistical analysis, including histogram generation, entropy, variance, and byte-transition analysis. Integrates with AXI DMA to overlap analytics with data movement, with implementations for PYNQ-Z1, ZCU104, and Alveo U55C.

zynq embedded-systems armv7 vivado pynq armv8 alveo armv7l vivado-hls xrt vitis bitstreams vitis-hls pyxrt

Updated Sep 2, 2026
VHDL

pg1590 / HLS-GEMM-Accelerators-on-AMD-Xilinx-FPGA

Matrix-multiply accelerators in Vitis HLS on an Alveo U50: tiling, systolic arrays, dataflow, double buffering, and INT8 quantization.

fpga hls xilinx hardware-acceleration gemm alveo vitis-hls systolic-array

Updated Aug 4, 2026
C++

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