computer-architecture-lab

Simple 8-bit CPU core in Verilog & Vhdl for Xilinx Spartan-6, featuring a custom instruction set, assembler, compiler, and simulation tools.

A complete modernization of the legacy 2005 MARS emulator. Upgraded into a state-of-the-art IDE featuring live C-to-MIPS cross-compilation, dynamic 5-stage pipeline visualization, and advanced hardware analytics.

Building a processor simulator for the ToyRISC Instruction Set Architecture, using Java, as part of the coursework for CS2160: Computer Organization Lab, IIT Palakkad

Advanced Computer Architectures - Practical Assignment #2: Create a shell script that sends custom jobs (thread & core level parallelized code) to an SGE cluster scheduler in order to execute an HPC NPB Benchmark, so we can study the performance impact on a shared-memory multiprocessor when emulating different processor cache architectures (vary…

Homeworks and course project of logic circuit and computer architecture laboratory are located in this repository

This contains my solution to the labs of Computer Architecture course for the year 2020-21

A ModelSim project that implements a MIPS single-cycle CPU using Verilog.

Computer Architecture Lab - Fall 2021

Assembly implementation of time quantum scheduling on x86, using two methods: software loops and hardware timer interrupts.

Study notes and resources for Computer Organization and Architecture (COA), covering digital components, computer arithmetic, CPU organization, memory, and I/O.

Computer Architecture Lab Exercises

This repository supports students taking Dr. Mehmood Qureshi’s Computer Architecture course. It enhances the open-source MARS simulator, simplifies the X-Ray Tool for register-level instructions, and includes an AI assistant to aid lab comprehension.

📚 In-depth Coursework, Reports, and Educational Resources for the Computer Architecture Laboratory Course at Urmia University.

A Java implementation of the Little Man's Computer (LMC) with interactive features

Implementing circuits through VHDL

A ModelSim project that implements a MIPS pipelined CPU in Verilog, enhancing efficiency through pipelining based on single-cycle CPU concepts.

A repository containing various assembly language programs for microcontrollers.

This repository contains the lab classes that were conducted to understand ARM architecture.